The present invention relates to a semiconductor integrated circuit device, and in particular to a technique which is especially effective in application to ASIC (application specific integrated circuits) memories comprising a plurality of bipolar transistor RAMs (random access memories) as basic constituents, for example. Bipolar transistor RAMs (hereafter referred to as bipolar RAMs) comprising bipolar transistor memory cells and cascade-connected ECL (emitter coupled logic) gate circuits (custom gates) as basic constituents are known. Further, there are also known ASIC memories comprising a combination of such bipolar RAMs and predetermined logic blocks.
Bipolar RAMs are described in JP-A-58-60487 published on Apr. 9, 1983, for example.
A semiconductor memory device comprising a plurality of RAM blocks and logic circuit blocks disposed near the RAM blocks is disclosed in U.S. Pat. No. 5,023,835 issued Jun. 11, 1991 and assigned to the same assignee as the present application and, which is a continuation application of U.S. patent application Ser. No. 13,550 filed on Nov. 2, 1987 and now abandoned.
In advance of the present invention, the present inventors developed an ASIC memory device as shown in FIG. 1. In FIG. 1, the ASIC memory device comprises six random access memories RAM0 to RAM5 comprising bipolar RAMs formed on one semiconductor substrate SUB, an input buffer IB1 for receiving a read selecting signal RS0-RS5 and a write selecting signal WS0-WS5 and generating an internal read selecting signal rs0-rs5 and an input write selecting signal ws0-ws5, an internal buffer IB2 for receiving an address signal A0-Ai and generating an internal address signal a0-ai, an input buffer IB3 for receiving a write data signal WD0-WDn and generating an internal write signal Wd0-Wdn, and an output data selecting circuit DSL for selectively outputting an output signal rd00-rd0n, rd10-rd1n, . . . , rd50-rd5n as a memory output signal RD0-RDn responsive to the internal read selecting signal rs0-rs5. On the substrate SUB, the input buffers IB1-IB3 are disposed nearly halfway between a side of the substrate where the input signals RS0-RS5, WS0-WS5, A0-Ai and WD0-WDn, and received and another side of the substrate where the memory output signal RD0-RDn is outputted, i.e., the input buffers IB1-IB3 are disposed nearly in the center of the arrangement of the random access memories RAM0-RAM5. The random access memory RAM0 RAM5 is started by the internal address signal a0-ai to start a predetermined read operation. Further, a corresponding internal write selecting signal ws0-ws5 is alternatively set at a high level to execute a predetermined write operation. In this ASIC memory device, the above described input buffers IB1-IB3 are disposed in the center of the random access memories RAM0-RAM5 as described above. Therefore, variations in propagation delay time taken for the input signals such as the address signal A0-Ai to reach respective random access memories are limited. The overall access time of the ASIC memory device is thus shortened equivalently.
As the performance of the digital system comprising an ASIC memory device is raised and an increase in storage capacity and a higher speed are demanded upon the ASIC memory device, it has been made clear that the following problems occur in the above described ASIC memory device. That is to say, in the above described ASIC memory, the input buffers IB1-IB3 for transferring the input signals such as the read selecting signal, the write selecting signal, the address signal and the write data signal are disposed in the center of the random access memories RAM0-RAM5 as described before. In the central portion of the ASIC memory device, therefore, an area having concentrated signal conductors is generated, and layout design for the memory device becomes complicated. Further, since respective signals are transferred via signal conductors which are not necessarily disposed in order of progress of signal processing operations, the overall signal conductor length of the ASIC memory device is increased and the propagation delay time is also increased. Further, there still remain variations in propagation delay time taken for input signals to reach respective random access memories. On the other hand, variations in propagation delay time taken for output signals of respective random access memories to reach the output data selecting circuit DSL tend to, on the contrary, increase because of the above described arrangement of the input buffers.
As shown in FIG. 2, access time t.sub.AC of this ASIC memory device is equivalent to the sum of the maximum value t.sub.ADX of address signal propagation delay time taken for the address signal to reach the random access memory RAM0-RAM5, the maximum value t.sub.RAX of RAM access time elapsing from the time when the internal address signal a0-ai is inputted to the random access memory RAM0-RAM5 until the time when the signal read out from the RAM0-RAM5 becomes valid, and the maximum value t.sub.ODX of output data propagation delay time taken for the output signal of the random access memory RAM0-RAM5 propagating to the output terminal of the output data selecting circuit DSL. Since variations still remain in the propagation delay time of respective signals and the overall delay time value is increased as described before, shortening of the access time t.sub.AC of the ASIC memory device is limited. As a result, enhancement in performance of a digital system comprising an ASIC memory device is limited.